Parity Generator Vhdl Program
I have completed a VHDL 16-bit parity generator and I would like to know if I have programmed it correctly. I have compiled it 10 times and worked out any bugs that it found. I was finally able to compile it successfully.
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My problem is that I am trying to run a timing simulation to make sure it will work correctly but I am not sure what I should be looking for. The basic operation is to XOR the A and B inputs to perform an iterative process with an output of '1' as odd and an output of '0' as even. My code is written such that a basic XOR block is then added as a component of the complete parity generator. I would like a second opinion to make sure I have written it correctly and if it will do what it is designed to do. I thank you all in advance and look forward to any input, good or bad. Basic XOR gate block VHDL Code library ieee; use ieee.stdlogic1164.all; entity xorgate is port( a: in stdlogic; b: in stdlogic; pari: in stdlogic; paro: out stdlogic); end xorgate; architecture behavior of xorgate is begin paro.
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Below figure shows VHDL program for parity generator. Line 13 shows the XOR operation on all input bits. Parity generator and Checker implementation in VHDL.
As mentioned in the comments the or part of your 'xorgate' prevents it from actually working as an xor gate to calculate bit parity. Instead your paro signal will be '0' when a=b and '1' when a/=b (the 16 bit vectors, not the bits within xorgate). If that was your intended functionality, then paro.